The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a storage electrode.
In recent years, as semiconductor devices become more and more integrated, a reduction in a design rule is being rapidly achieved. Accordingly, there is a need to implement an ultra fine pattern. In particular, in order to secure a process margin in a memory device such as a dynamic random access memory (DRAM) device, a procedure disposing a dummy pattern around a real pattern is recognized as an important factor.
FIG. 1 is a layout view illustrating an exposure mask for a storage electrode according to the related art. Referring to FIG. 1, the exposure mask 100 is used to form a storage electrode region. A plurality of first transparent patterns 105 defining a storage electrode region are provided. A second transparent pattern 110 having a critical dimension CD(d1) larger than a CD(d2) of the first transparent pattern 105 in an outermost zone of the cell region. Since patterns formed at the outermost zone is weak in an exposure process, the pattern CD on the exposure mask is formed larger than that of a CD of a final desired pattern.
In a conventional method for manufacturing a semiconductor device as described above, a process margin in decreased due to a difference in CD of a storage electrode region formed at a middle part of the cell region and a CD of a storage electrode formed at the outermost zone of the cell region. Accordingly, when forming the storage electrode, a bunker defect and column fail can occur due to an inaccurate Self Aligned Contact (SAC) process between the storage electrode and a bit line. These defects deteriorate the characteristics of the semiconductor device.